Publication 1747-2.39SLC 500™ Chassis–Based Processors(Catalog Numbers 1747–L511, –L514, –L524, –L531, –L532, –L541, –L542, –L543, –L551, –L
10 SLC 500™ Chassis–Based Processors Publication 1747-2.39The table below summarizes the SLC 500 processor channel connections.Protocol OptionsEther
SLC 500™ Chassis–Based Processors 11 Publication 1747-2.39Data Highway Plus (DH+) ProtocolThe Data Highway Plus protocol is used by the PLC–5
12 SLC 500™ Chassis–Based Processors Publication 1747-2.39System Protection OptionsThe SLC 500 family of processors offer a number of hardware and s
SLC 500™ Chassis–Based Processors 13 Publication 1747-2.39I/O UsagesThe SLC 500 family of processors support a variety of I/O modules, allowi
14 SLC 500™ Chassis–Based Processors Publication 1747-2.39Programming InstructionsThe following programming instructions are used with the SLC 500 p
SLC 500™ Chassis–Based Processors 15 Publication 1747-2.39Comparison InstructionsInstruction Mnemonic and NameExecution Times (µs) Floating P
16 SLC 500™ Chassis–Based Processors Publication 1747-2.39Math InstructionsInstruction Mnemonic and NameaExecution Times (µs) Floating Point (µs) b
SLC 500™ Chassis–Based Processors 17 Publication 1747-2.39SWP Swap ——24 + 13.09 per word22.6 + 12.13 per wordSwaps the low and high bytes of
18 SLC 500™ Chassis–Based Processors Publication 1747-2.39Data Handling InstructionsInstruction Mnemonic and NameExecution Times (µs) Floating Point
SLC 500™ Chassis–Based Processors 19 Publication 1747-2.39Program Flow InstructionsInstruction Mnemonic and NameExecution Times (µs)Function
2 SLC 500™ Chassis–Based Processors Publication 1747-2.39Features and BenefitsSupports user memory sizes from 1K to 64K. By offering a wide range of
20 SLC 500™ Chassis–Based Processors Publication 1747-2.39Application Specific InstructionsCommunication InstructionsProportional Integral Derivativ
SLC 500™ Chassis–Based Processors 21 Publication 1747-2.39ASCII InstructionsInstruction Mnemonic and NameaExecution Times (µs)Function - Outp
22 SLC 500™ Chassis–Based Processors Publication 1747-2.39Interrupt Routine InstructionsIndirect AddressingThe following sections describe how indir
SLC 500™ Chassis–Based Processors 23 Publication 1747-2.39Execution Times for Word–Level Indirect AddressesFor most types of instructions tha
24 SLC 500™ Chassis–Based Processors Publication 1747-2.39Execution Times for Bit–Level Indirect AddressesIndirect bit addresses are based on the fo
SLC 500™ Chassis–Based Processors 25 Publication 1747-2.39Instruction Execution TimesExecution Time Example - Bit Instruction Using an Indire
26 SLC 500™ Chassis–Based Processors Publication 1747-2.39The following table summarizes the communication options for the SLC 500 processor family.
SLC 500™ Chassis–Based Processors 27 Publication 1747-2.39The following table summarizes the general specifications for the SLC 500 processor
Publication 1747-2.39 - December 1997 Supersedes Publication 1747-2.39 - December 1995 1998 Rockwell International. All Rights Reserved. Printed in U
SLC 500™ Chassis–Based Processors 3 Publication 1747-2.39Supports a host of third–party products through the Allen–Bradley Encompass Program.
4 SLC 500™ Chassis–Based Processors Publication 1747-2.39SLC 5/03™ Processor (Catalog # 1747–L531 and 1747–L532)The SLC 5/03 processor significantly
SLC 500™ Chassis–Based Processors 5 Publication 1747-2.39SLC 5/04™ Processor (Catalog # 1747–L541, –L542, or –L543)The SLC 5/04 processor pro
6 SLC 500™ Chassis–Based Processors Publication 1747-2.39SLC 5/05™ Processor (Catalog # 1747–L551, –L552, or –L553)The SLC 5/05 processor provides i
SLC 500™ Chassis–Based Processors 7 Publication 1747-2.39System ThroughputWhen your application requires high–speed processing it requires mo
8 SLC 500™ Chassis–Based Processors Publication 1747-2.39Interrupt SubroutinesThe following interrupt subroutines allow you to provide predetermined
SLC 500™ Chassis–Based Processors 9 Publication 1747-2.39Communication OptionsThe SLC 500 processors support different types of communication
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